1. Field of the Invention
This invention relates generally to integrated circuit memory devices and methods of operation therefor and, more specifically, the invention relates to CMOS read-only memories.
2. Description of the Prior Art
In the past, read-only memories (ROM's) have been implemented in a variety of integrated circuit technologies. With the advent of large scale integrated (LSI) circuits in the MOS format, most prior art ROM's have utilized the N-channel conductivity type devices as opposed to P-channel conductivity type devices because of the increased speed performance possible with the former.
There remains an unfulfilled need for integrated circuit ROM's of lower power consumption. On a theoretical basis, at least, this need may be filled by complementary MOS device ROM's. However, the N-channel device configurations used heretofor in MOS LSI circuits are not particularly suited for the achievement of high density in the row-column array organization of a typical memory.
The companion application hereinbefore cited described improved complementary MOS devices for achieving an integrated circuit memory which operates at least internally with very low currents so that small device sizes may be achieved. In particular, the companion application described devices which have very high packing density for the achievement of memory devices with a high capacity.
This application describes methods for operating a memory device which take full advantage of the performance improvements provided by the devices described in the companion application. In accordance with the methods and the particular circuits described, the achievement of the full capability of the improved devices in a CMOS ROM having low power dissipation is enabled.